>
Video: Spacious bubble-sub lets you tour the sea floor in first class
NASA just hacked a 1977 computer on a spacecraft way out past Pluto
First-ever autonomous motor race streams live this weekend
Kanye West plans to launch Yeezy PORN studio with Stormy Daniels' ex in latest shock move...
Blazing bits transmitted 4.5 million times faster than broadband
Scientists Close To Controlling All Genetic Material On Earth
Doodle to reality: World's 1st nuclear fusion-powered electric propulsion drive
Phase-change concrete melts snow and ice without salt or shovels
You Won't Want To Miss THIS During The Total Solar Eclipse (3D Eclipse Timeline And Viewing Tips
China Room Temperature Superconductor Researcher Had Experiments to Refute Critics
5 video games we wanna smell, now that it's kinda possible with GameScent
Unpowered cargo gliders on tow ropes promise 65% cheaper air freight
Wyoming A Finalist For Factory To Build Portable Micro-Nuclear Plants
TSMC was the first company to use ASML's EUV lithography machines for high-volume production and now has at least three processes that use EUV for select layers. They use EUV lithography for its N7+, N6, and N5 nodes.
TSMC's 2nd generation 7 nm technology (N7+) uses EUV for up to four layers in order to reduce its use of multi-patterning techniques when building highly complex circuits. The 6 nm process (N6) is for customers to re-use IP designed for 1st generation 7 nm, per the report. TSMC's 5 nm process (N5) can use EUV for up to 14 layers. 5nm has significant increase in transistor density and performance enhancements.
2nd generation 5 nm (N5P) and 4 nm (N4) fabrication processes are based 5 nm technology and will have performance and power benefits. N5P will be available in 2021. N4 chips will have volume production in 2022.
Next-generation 3 nm process (N3) will be a full node improvement over N5. N3 will have 70 percent logic density gain, 15-percent performance gain, and 30-percent power reduction over the 5-nm process. N3 will use EUV over 20 layers.
Nextbigfuture covered Taiwan Semiconductors plans from 2017. TSMC has kept on track with its Moore's Law roadmap to reach 3-nanometer chips by 2022.